Cte compensation for wafer-level and chip-scale packages and assemblies

ABSTRACT

CTE compensation for wafer-level and chip-scale packages and assemblies.

RELATED APPLICATIONS

This application is a continuation in part of U.S. application Ser. No.15/498,188, filed on Apr. 27, 2017, which claims the benefit of priorityof U.S. Provisional Application No. 62/327,807, filed on Apr. 26, 2016,the entire contents of which application are incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates generally to the field ofmicroelectronics, and more particularly to methods for compensating fordifferences in the coefficient of thermal expansion (“CTE”) in differentmaterials used in wafer-level and chip scale packaging of semiconductordevices, especially high frequency (RF) semiconductor devices.

BACKGROUND OF THE INVENTION

As semiconductor technology advances, and more active semiconductorfunctionality is packed into smaller silicon real estate, the packagingand passives costs, especially in RF devices, increase compared to theoverall cost of the device. To decrease the cost, wafer-level packaging(“WLP”) is becoming a more practical and more cost-effective approach.However, the cost savings associated with wafer-level packaging comes atthe expense of performance, especially in RF devices.

In some approaches, RF passives are either built sequentially over thesurface of the wafer, either on the usable semiconductor substrate area,or on another dielectric substrate deposited over the semiconductorwafers; or built on another substrate in parallel, and then joined overthe semiconductor wafer containing active circuitry. Regardless of themethod used to realize semiconductor devices such as those disclosedherein, CTE mismatch between the semiconductor substrate and passivematerials, such as dielectrics and metals, is a major issue. Usually,matching of the CTE causes sacrifices in the quality factor (Q factor)and dielectric properties for high frequency devices. Traditional orcurrent approaches to integrate antennas directly with microchipsinvolve planar circuits, multi-layer glass stacks, BCB, polyimide orother technologies either bonded to or directly integrated on thesemiconductor substrate. These options may create their own CTEchallenges.

In cases where dissimilar microelectronic substrates are to be joinedtogether at large die format or wafer-to-wafer level format, the CTEmismatch between adjacent substrates can render this effort eitherimpossible or create significant additional cost due to part damage orfailure including substrate deformation. Similarly, for a sequentialbuild of metallic circuitry on a low CTE semiconductor wafer orsubstrate, such as a PolyStrata® coaxial transmission line build, thisCTE mismatch is problematic.

SUMMARY OF THE INVENTION

In one of its aspects the present invention relates to methods andstructures to allow cost effective wafer level packaging ofsemiconductor die to turn the structures into chip scale packages at thewafer level. In addition, the present invention can address the CTEmismatch problem that occurs in applications ranging from wafer levelpackaging for memory or other chips, to antenna circuitry made in aprimarily copper PolyStrata® process that is formed on, or attached to,semiconductors, such as to SiGe circuits on silicon substrates, atscales normally not possible due to the CTE mismatch between these tworelatively rigid formations. (Examples of PolyStrata°processing/technology are illustrated in U.S. Pat. Nos. 7,948,335,7,405,638, 7,148,772, 7,012,489, 7,649,432, 7,656,256, 7,755,174,7,898,356 and/or U.S. Application Pub. Nos. 2010/0109819, 2011/0210807,2010/0296252, 2011/0273241, 2011/0123783, 2011/0181376, 2011/0181377,each of which is incorporated herein by reference in their entirety,hereinafter the “incorporated PolyStrata® art”). This may be achieved byapplying flexible CTE compensating regions between unit cells into theprimarily copper formations to reduce the propagation of stress acrosslarge CTE mismatched areas of two or more bonded regions. This approachmay work independent of the structures being formed separately andjoined, or formed one upon the other. A three-dimensional copper springstructure is envisaged by using PolyStrata® fabrication technology andother manufacturing techniques.

In another of its aspects, the present invention may provide anmicroelectronic structure having CTE compensation for use in wafer-leveland chip-scale packages. The microelectronic structure may include aplurality of substrate tiles each having a generally planar uppersurface, the upper surfaces of the tiles disposed within a common planeto provide a generally planar grid of the tiles. Each respective pair ofadjacent tiles may have a gap disposed therebetween and a springstructure spanning the gap and connecting the adjacent tiles. The springstructure may be configured to permit movement of the adjacent tilesrelative to one another to provide compensation for thermal expansion orcontraction of the tiles. The substrate tiles may comprise asemiconductor material and/or metal. The spring structure may comprisemetal, and may be provided in the form of a membrane and/or a2-dimensional serpentine structure. In one particular configuration, thespring structure may be a u-shaped membrane having a longitudinal axisthat is disposed parallel to an edge of the upper surface of theselected tile to which the u-shaped membrane is attached. In addition, adielectric material may be disposed on the common plane and within thegap. A device layer may be attached to the common plane, and the layermay include one or more of resistors, capacitors, inductors, andthree-dimensional metal/dielectric structures. The three-dimensionalmetal/dielectric structures may include one or more of coaxialwaveguides, antennas, Wilkinson combiner/dividers, Gyselcombiner/dividers, and filters. The plurality of tiles may each comprisemultiple layers of metal disposed parallel to the upper surface, whichmay result from formation using a multilayer build process, such as thePolyStrata° process. Microelectronic structures of the present inventionmay include antenna arrays having a plurality of antenna radiatorstructures disposed above the upper surfaces of the tiles.

In yet another of its aspects, the present invention may provide amethod of forming a three-dimensional microstructure by a sequentialbuild process, comprising disposing a plurality of layers over asubstrate, wherein the layers comprise one or more layers of aconductive material and one or more layers of a sacrificial material,thereby forming a structure above the substrate. The structure mayinclude a plurality of conductive tiles formed of the conductivematerial, each tile having a generally planar upper surface, the uppersurfaces of the tiles disposed within a common plane to provide agenerally planar grid of the tiles, each respective pair of adjacenttiles having a gap disposed therebetween and a spring structure spanningthe gap and connecting the adjacent tiles. The spring structure may beconfigured to permit movement of the adjacent tiles relative to oneanother to provide compensation for thermal expansion or contraction ofthe tiles. In addition the method may include removing the sacrificialmaterial and/or the substrate. The step of disposing a plurality oflayers over a substrate may include disposing one or more layers of adielectric material. In addition, the method may include electricallyconnecting a device layer to the common plane. The device layer maycomprise one or more of resistors, capacitors, inductors, andthree-dimensional metal/dielectric structures, such as coaxialwaveguides, antennas, Wilkinson combiner/dividers, Gyselcombiner/dividers, and filters.

In still a further of its aspects, the present invention may provide amethod of forming a three-dimensional microstructure by a sequentialbuild process, such as the PolyStrata® process. The method may includeproviding a substrate having opposing upper and lower surfaces, with atrench extending from the lower surface to a region proximate the uppersurface; providing a stretcher layer on the trench and lower surface ofthe substrate; expanding the stretcher layer linearly along a directionparallel to the lower surface of the substrate to separate the substrateinto first and second substrate portions divided at the location of thetrench providing an expanded trench region; and providing a dielectricmaterial in the expanded trench region. The step of providing adielectric material may include providing the dielectric material on theupper surface of the first and second substrate portions. A plurality ofconductive vias may be provided through the dielectric material, and thevias may be in electrical communication with the upper surface of atleast one of the first and second substrate portions. A device layer maybe provided over the dielectric material, the device layer including atleast one electronic component in electrical communication with aselected one of the vias.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing summary and the following detailed description ofexemplary embodiments of the present invention may be further understoodwhen read in conjunction with the appended drawings, in which:

FIGS. 1-4 schematically illustrate cross-sectional views of some of thecommon approaches currently used in wafer fabrication;

FIGS. 5-10 schematically illustrate cross-sectional views of anexemplary process and wafer configuration having reduced CTE mismatch inaccordance with the present invention, in which

FIG. 5 schematically illustrates a wafer with a connecting regionbetween dice and a thinned substrate region on an opposing surface wherethe dice will be separated,

FIG. 6 schematically illustrates FIG. 5 after a material is depositedwhich may have selective adhesion to differing regions of the wafer butkeeps the wafer together after the substrate is fragmented intoelements,

FIG. 7 schematically illustrates FIG. 6 after the wafer material isseparated (made discontinuous) between die,

FIG. 8 schematically illustrates FIG. 7 after the wafer is expanded anddie separated as the material 400 is stretched along the plane of thewafer,

FIG. 9 schematically illustrates FIG. 8 after the wafer is overcoatedwith a material to create a spacer region between die, which overcoatmay be of a different CTE than the wafer, and

FIG. 10 schematically illustrates the overcoat material of FIG. 9 aftervias are formed therethrough and passives or contact pads are createdthereon;

FIGS. 11-12 schematically illustrate cross-sectional views of anexemplary spring-like formation in accordance with the present inventionthat may be provided at the wafer level with a substrate portion removedproximate the formation, with FIGS. 11A-11F showing an exemplary processfor the making thereof;

FIG. 13 schematically illustrates a typical existing chip-scale packagewith the contacts redistributed from the front surface of the die to aback surface of a substrate in the form of solder balls for surfacemounting;

FIG. 14 schematically illustrates a cross-sectional view of wafer levelchip scale packaging in accordance with the present invention using thedie configuration of FIG. 8, where a back surface of a substrateincludes solder ball contacts for surface mounting;

FIGS. 14A-14G schematically illustrate cross-sectional views of anexemplary method in accordance with the present invention for formingthe wafer level chip scale package of FIG. 14;

FIG. 15 schematically illustrates a simplified top-isometric view of athree-by-three array of ground plane tiles connected by U-shaped springfeatures and a detailed view of the U-shaped spring structures inaccordance with the present invention;

FIG. 16 schematically illustrates a bottom isometric view of the arrayof ground plane tiles of FIG. 15;

FIG. 17 schematically illustrates a top view of the array of groundplane tiles of FIG. 15;

FIG. 18 schematically illustrates a cross-sectional view of an antennaarray joined using CTE-decoupling features in accordance with thepresent invention, and associated

FIGS. 18A-18O schematically illustrate cross-sectional views of anexemplary method in accordance with the present invention for creatingthe structure of FIG. 18;

FIG. 19 schematically illustrates the antenna array of FIG. 18 attachedto a semiconductor chip or wafer;

FIG. 20 schematically illustrates a top view of two-dimensional-springconnected ground plane tiles in accordance with the present invention;

FIG. 21 schematically illustrates cross-sectional views of a version ofthe structure of FIG. 18 with staggered features to increase overallradiation shielding effectiveness; and

FIGS. 22A, 22B schematically illustrate cross-sectional views of asingulation technique in accordance with the present invention showingits use in creating an antenna array similarly structured to that ofFIG. 18.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the figures, wherein like elements are numbered alikethroughout, in one of its aspects the present invention providesstructures and methods for alleviating CTE mismatch betweensemiconductor substrates or wafers and components mounted or formedthereon. For example, FIGS. 1-4 illustrate existing conventionalstructures which suffer from CTE mismatch among components notincorporating the improvements of the present invention, butdemonstrating the need for such improvements. In particular, FIG. 1illustrates a semiconductor wafer 100 comprising two adjacent dice 102,104 with electrodes 106 mounted on an upper surface of the wafer 100.Often additional structures are subsequently provided on the uppersurface of the wafer 100, and those additional structures can comprisematerials which have a CTE significantly different from that of thewafer 100.

For example, FIGS. 2 and 3 illustrate a spacer 200 provided on the uppersurface of the wafer 100 through which conductive vias 202 are formed.The vias 202 may be filled with the metal, such as by a plating process,to provide electrical connection to the electrodes 106 encased withinthe spacer 200. Additional electronic components 300, such as a layer ofpassives, may be provided on top of the spacer 200, and placed inelectrical communication with the metal filled vias 202. The passives300 may include capacitors, resistors, inductors, impedance matchingcircuits, or may be many layers of patterned metals such as copper,dielectrics, and air or void has been described in the art ofPolyStrata® processing as practiced by Nuvotronics, Inc. and describedin Nuvotronics' patents.

The spacer 200 can be a low loss dielectric material which, besidesimproving the Q-factor, also alleviates/decreases the sources ofinterference between the passives 300 and active circuitry of thesemiconductor wafer 100, as well as the ground plane.

Whether the spacer 200 is built sequentially or in parallel and attachedto the semiconductor wafer 100 later as shown in FIG. 4, the CTEmismatch between the wafer 100 and the material of the spacer 200 isalways a significant problem. (More particularly, FIG. 4 illustrates thesituation where the passives 300 and interconnect 210 to the wafer 100are formed independently and then bonded to the wafer 100 in sequentialsteps using any suitable methods such as Au-Au compression, solder,epoxy, and so on. Handle wafers that may be used in this process are notshown for simplicity as many variations are known and practiced in theart of wafer level packaging.)

The layers of interconnects 210, passives 300, and dielectric spacer 200typically have a CTE that does not match the CTE of semiconductor orceramic materials which may comprise the wafer 100. The metals anddielectrics present in the spacer 200 and passives 300 are usuallyseveral to 10 times or more the CTE of the wafer 100. This CTE mismatchcan cause many problems including wafer bow or wafer breakage andfundamentally limits the thickness and reliability over temperature ofthe spacer 200 and passives 300 when formed or joined with or on thewafer 100. Such CTE mismatch also limits the size of the chip or wafer100 that can be formed for any such contiguous structures. Thus, the CTEmismatch between wafer 100 and spacer 200 presents a serious problemthat could cause the entire wafer 100 to bulge, curl or even break.

Applicant has recognized that there is a serious need for structures andmethods to decouple the stress and strain in such devices. Such asolution is important to both wafer level packaging and chip scale andwafer scale solutions, e.g., for applications such as phased arrays,which often need complex antenna solutions and distribution networksthat are interconnected down to pads and/or active devices formed in oron the semiconductor wafer 100.

As a result, in one of its aspects, FIGS. 5-12 schematically illustrateexemplary approaches in accordance with the present invention to addressthe CTE mismatch problems between semiconductor wafer and theinterconnect and passive structures. FIG. 5 illustrates a wafer 100comprising two adjacent dice 102, 104 along with electrodes 106 disposedon an upper surface 115 of the wafer 100. A portion of the wafer 100 isremoved in a trench region 108 between the dice 102, 104 to assist withfuture separation of the dice 102, 104 in a manner that ameliorates CTEmismatch in accordance with the present invention. The trench region 108may be provided in the form of a trench having sidewalls 116 that may beformed either chemically or by dry etching, and may desirably be placedaround saw lines of every die, or clusters of dice, on the wafer 100.The trench region 108 of removed wafer material may extend upwardlyproximate to the upper surface 115 of the wafer 100 but not reach thesurface 115, to keep the wafer 100 in one piece, FIG. 5. To assist inthis regard, etching of the trench region 108 may be stopped by adeposited stop layer 110 of oxide, nitride, metal or polymer depositedon the upper surface 115 of the wafer 100 in the vicinity of the upperextent of the trench region 108. The stop layer 110 may comprise asimilar or different material from that of the electrodes 106. In thecase where the removal of wafer material in the trench region 108extends all the way to the upper surface 115, it may be desirable thatthe stop layer 110 be sufficiently mechanically strong to hold the twodice 102, 104 together while maintaining the upper surfaces 115 of eachdice 102, 104 in the same plane.

Once the trench region 108 of removed wafer material is formed, astretcher material 400, such as Parylene, may be disposed on the backsurface 117 of the wafer 100, FIG. 6. In one exemplary approach inaccordance with the present invention, selective adhesion of thestretcher material 400 may be used. Selective adhesion could beachieved, for example, by depositing an adhesion promoter to the backsurface 117 of the wafer 100, while preventing the deposition of theadhesion promoter to the sidewalls 116, such as by masking the sidewalls116. Alternatively, the sidewalls 116 may be treated or formed in a waythat lessens adhesion of the stretcher material 400 to the sidewalls116.

In preparation for separation of the adjacent dice 102, 104 from oneanother, the stop layer 110 may be removed, and the two dice 102, 104may be maintained in the original planar relationship relative to oneanother by the stretcher material 400 and/or a portion of the wafer 100that remains intact above the trench region 108. To separate theadjacent dice 102, 104, a portion 112 of the wafer 100, locatedproximate the trench region 108 of removed wafer material, may beremoved using either chemical or dry etch, a laser, or dicing removal,for example, FIG. 7. Thereafter, the wafer 100 may be stretched usingdie matrix expansion with slight force to break the poor adhesionbetween the stretcher material 400 and the sidewalls 116, thusseparating each die 102, 104 on the wafer 100, while the stretchermaterial 400 still preserves the separated dice 102, 104 as a planarstructure similar in planarity to that of the original wafer 100, FIG.8. The expanded wafer 100 from this point on can still be handled as awafer with precise X-Y-Z coordinates for each die 102, 104. Depending ofsemiconductor substrate thickness, the wall angle of the trench region108, and the stretching capabilities of the material 400, one canincrease the overall size of the semiconductor wafer 100 to provideadditional real estate over the semiconductor dice, e.g., for buildingmore passives. Some stretcher materials such as Parylene C can stretchup to 200% of their length. Additionally even without any stretching ofthe stretcher material 400, delaminating the stretcher material 400 fromthe sloped walls 116 will extend the x-y dimensions between each dice by2× length of a single sloped wall 116.

Further processing can include depositing a spacer material 500 in theregion 109 between the two dice 102, 104 as well as on the upper surface115 of the wafer 100. The CTE of the spacer material 500 may closelymatch the CTE of the stretcher material 400 and/or have a CTE largerthan that of the wafer 100. In such a configuration, the CTE mismatchmay still be present, but in this case the CTE mismatch can propagateonly over the area of each single die 102, 104, which even at 200° C.with a CTE difference of 50 PPM/° C. between the wafer 100 and spacermaterial 500, is only 2 microns over the areas of a 1 cm×1 cm die, inX-Y dimensions. As a result, the wafer 100 can remain flat and free ofstress throughout any of the subsequent process steps.

For example, subsequent process steps can include providing vias 602through the spacer material 500 to electrically communicate withrespective ones of the contacts 106, FIG. 10. A further layer 600 mayalso be provided on the spacer material 500 and may include electroniccomponents, such as passives, e.g., resistors, capacitors, inductors, inelectrical communication with the vias 602. Alternatively oradditionally, the layer 600 may include three-dimensionalmetal/dielectric structures, such as coaxial waveguides, antennas,Wilkinson or Gysel combiner/dividers, and filters, formed by the PolyStrata® fabrication processing (Nuvotronics, Inc., Virginia, USA). In afurther exemplary configuration for lowering CTE while maintainingwafer-level planarity between adjacent dice 142, 144 in accordance withthe present invention, FIGS. 11, 12 schematically illustrate twoadjacent dice 142/144, 152/154 of a wafer 100 with a 3D spring membrane700 disposed around the periphery of each dice 142/144, 152/154 on thewafer 100. The membrane 700 may act as a spring or CTE cushion to absorbthe CTE mismatch that may occur as additional materials are added, suchas spacer materials 200, 500 or additional layers 300, 600 like thoseillustrated and discussed in connection with FIGS. 1-10. Placement ofthe membrane 700 at the periphery of each die allows any CTE mismatch topropagate along each die 142, 144, 152, 154, instead of having the CTEmismatch propagate over the entire wafer 100, thereby stressing,bulging, and/or cracking the wafer 100. The membrane 700 can be a metalsuch as copper, a dielectric such as a low stress silicon nitride, or apolymer such as Parylene, benzocyclobutene (BCB) or polyimides, whichcan keep the wafer 100 in one piece but move and give way under CTEinduced expansion.

The structure of FIG. 11 may be made by a process flow as shown in FIGS.11A-11F to create a 3-D membrane 700 connecting each die 142, 144. FIG.11A shows a beginning substrate is used, such as a silicon wafer 100.FIG. 11B shows that a hard mask 162 is provided having a hole 163through which the wafer 100 may be crystallographically etched <100>using crystallographic silicon planes to create an etched hole 165, FIG.11C. The mask 162 is stripped, as shown in FIG. 11D. Metallization isplaced on the wafer 100, including in regions of the etched hole 165,which form a membrane 700 and optionally contacts 106, FIG. 11E. Themembrane 700 may be thick copper (10 or more microns) or a polymer orany suitable material. The back side of the wafer 100 may then beprocessed using (for example) dry etching from the backside to singulatethe dice 142, 144, leaving them connected by the membrane 700, FIG. 11F.A similar process may be used to create the structure of FIG. 12 inwhich steps 11A-11E are repeated, but wet etching on thecrystallographic planes is used to singulate the dice 152, 154 insteadof the dry etching of FIG. 11F.

In yet another of the aspects of the present invention, the structuresof FIG. 8 may be leveraged to utilize the aforementioned increased realestate created by the separation of dice on the stretcher material 400.For example, the increased real estate affords a number of possibilitiesfor making chip scale packages at the wafer level.

Chip scale packages are usually processed in strip or lead frame formatusing singulated dice, since the size of a chip scale package isslightly larger than the die size, due to industry definitions and thefact that the wire bond locations on the tape have to extend beyond theactual size of the die. FIG. 13 shows a typical existing Chip ScalePackage (“CSP”) including a semiconductor chip 3001, wire bonds 3009,traces 3005, and solder ball contacts 3010. Using the concept ofexpanding the wafer size, shown in FIGS. 5-8, one can further processthe deposited material 400 at the back 117 of the wafer 100 to createmetallization, bonding pads and solder pads.

For instance, FIG. 14 illustrates an example of a CSP 800 in accordancewith the present invention formed at the wafer or grid level. The waferlevel CSP 800 includes electrodes 106, dice 102, 104, and a stretchermaterial 400 configured in a similar way as previously discussed withregard to FIGS. 5-8. In addition, an opening 3008 may be provided in thestretcher material 400 to permit wire bonds to electrically communicatebetween electrodes 106 and traces 3005 disposed on a dielectricsubstrate 3004. Solder pads 3010 may also be provided in electricalcommunication with the traces 3005 to complete the electricallyconductive pathway from the top side of the CSP 800 and electrodes 106to the bottom side of the CSP 800 and the solder pads 3010.

FIGS. 14A-14F represent exemplary process flow steps by which the CSP800 may be fabricated. Starting with FIG. 14A, a stretched wafer 3000 isprovided having a configuration similar to that shown in FIG. 8. Thestretched wafer 3000 includes two adjacent dice 102, 104 adjoined andsupported in a wafer-level planar fashion by a stretcher material 400.One or more electrodes 106 may be provided on each of the dice 102, 104.In this particular configuration the stretcher material 400 may be adielectric, selected to have nonconductive properties to be compatiblewith the remainder of the structure in the CSP 800. FIG. 14B shows aseparate base substrate 3000B with metallic traces 3005 and pads 3011disposed on a dielectric material 3004, which may be supported on adimensionally stable substrate carrier 3007. A sacrificial layer 3006may be provided between the substrate carrier 3007 and dielectricmaterial 3004 to facilitate removal of the carrier 3007 later.

The stretched wafer 3000 and the base substrate 3000B may be attached toeach other using the dielectric stretcher material 400 or by adding anadhesive there between, FIG. 14C. A portion of the dielectric stretchermaterial 400 may be removed in the region 3008, such as by plasmaetching, laser removal, or other suitable means for example, to exposeend portions of the traces 3005, FIG. 14D. Then, wirebonds 3009 may beprovided between the electrodes 106 and traces 3005 to provideelectrical communication therebetween, FIG. 14E. FIG. 14F shows theremoval of the dimensionally stable substrate carrier 3007, and FIG. 14Gshows that solder balls 3010 may be placed at the wafer-level on thebackside of the wafer assembly shown in FIG. 14F. It is further possibleto test these packaged assemblies at the wafer-level prior to dicing orsingulation of the chip-scale packaged devices. Also, lids may beapplied to the wafer-level packaged devices.

In addition variations of the above structures shown in FIGS. 5-8 may beprovided in accordance with the present invention, where a material canbe applied at the side of the wafer 100 where the trench region 108 islocated. The trench region 108 may be formed either from the front sideor back side of the wafer 100, and then traces can be formed on thesloped sidewalls 116, where instead of wire bonds one can directlyextend conductive trace metallization from one side of the wafer 100 tothe other side, or onto a substrate on either side of the wafer 100,thus scaling the X-Y dimensions of the wafer 100, while still keepingthe process at wafer level, for parallel and cost effective processes.This is merely one example in accordance with the present invention ofhow the stretching mechanism could be used for electronic devicefabrication and packaging.

The approach of creating a spring membrane 700 between cells or dice toform a structure that can be reliably bonded to another structure thathas a different CTE can be applied to various problems. For example inthe art of PolyStrata technology (typically copper structures), it maybe desirable to connect an antenna and/or feed and filter andmicro-coaxial device structures to non-CTE matched circuits such assemiconductor wafers or large die or ceramic modules. When formingantenna arrays having a continuous ground plane for the antenna array;however, it may be required to create a larger area that may be formedin a CTE mismatched material, such as copper, to be joined for exampleto a silicon wafer using silicon germanium (SiGe) as the activesemiconductor material, for high frequency applications.

FIGS. 15-17 schematically illustrate another exemplary structure inaccordance with the present invention—an array 1100 of ground planetiles 1102 forming an electrically continuous ground plane with signalconductors 1104 that pass through each ground plane tile 1102 and one ormore ground conductors 1106 mounted on, and electrically connected to,the ground plane tiles 1102. The signal conductors 1104 may be suspendedusing dielectric supports 1108 which may be a thermally conductiveceramic and may be embedded into the ground plane tiles 1102, FIG. 17.The dielectric supports 1108 may be strips partially embedded in thesignal conductor 1104, but could be membranes or shaped differently.FIG. 16 shows a bottom isometric view of the array 1100 of ground planetiles 1102 with the ground connections 1106 for connection to asemiconductor chip (e.g., a chip having a significantly lower CTE thancopper). There could be as many as eight or more ground connections 1106around each signal conductor 1104, or there could be as few as one ortwo, depending on the required impedance matching, design rules andother possible factors. In addition, the unit cells 1102 could houseother circuits (whether passive or active) therein.

The ground plane tiles 1102 (collectively the ground plane) of thethree-by-three array 1100 may be electrically connected byCTE-decoupling membranes 1112, in this case formed as U-shaped springs1112. The gap between the ground plane tiles 1102 and signal linefeedthrough, as well as the dimensions of the conductors 1104, can beelectromagnetically designed, simulated and optimized with software suchas HFSS™ or CST™ to ensure the signals or RF power may move fromstructures above the ground plane tiles 1102, such as antennas, tostructures below the ground plane tiles 1102, such as semiconductordevices on or in or even below a wafer/chip region connected to thesestructures. Creating designs with such software can minimize impedancemismatch causing reflections and power loss. The ground plane tiles 1102may be formed by PolyStrata® technology, comprising beam formingpassives, that may include couplers, baluns, filters, splitters,combiners, and so on.

Although one signal conductor 1104 is shown centered in each groundplane tile 1102, multiple signal conductors 1104 could pass through eachground plane tile 1102, such as a pair of differential lines for asingle polarization antenna or four feeds for a pair of differentiallyfed orthogonal polarizations. While the U-shaped spring regions 1112cause local deviations from the flat conductive ground plane, byminimizing their electrical length, the antenna ground plane can looklike an electrically-continuous ground plane operating to highfrequencies. In addition to U-shaped spring regions 1112 extending intothe positive Z direction, the spring regions 1112 could extend into thenegative Z direction. Also, the spring regions 1112 could be ‘V’ shaped,or repeat in sequence, or use different suitable shapes. Thus, thepresent invention allows one to join two otherwise-CTE-mismatchedstructures, because at least one of the structures is comprised of unitcells 1102 that are connected by regions 1112 that behave as springs. Ifthe thickness of the metal membranes 1112 is chosen properly, themembranes 1112 will contract and expand against the thermal expansion ofcopper, thus decoupling all or most of the thermal expansion inducedstress from adjacent terminals, e.g., signal conductor 1104 and groundconnections 1106, on each array element 1102. That is, the CTEmismatched structure(s) (for example a semiconductor wafer andPolyStrata® passives) mounted on the array of unit cells 1102 no longerbehave as rigid bulk slab(s) of different CTE being bonded together.

An exemplary use of the ground plane array 1100 of the present inventionis a wafer-scale phased array. FIG. 18 schematically illustrates across-sectional view of an antenna array 1800 comprising the groundplane array 1100 of FIG. 15 with the addition of antenna emitters 1110.

In general, wafer-scale phased arrays include electronic circuitrybehind each antenna element to provide beam steering and signalamplification and are of roughly the same size as the unit cell of theantenna element, which is generally approximately half of a wavelengthat the upper end of the frequency of operation, but may be less or moredepending on the electronic scanning requirements of the particularapplication. Such an architecture eliminates some levels of packagingand testing and may be a best method of making phased arrays at uppermillimeter-wave frequencies. For wafer-scale arrays, precisiondefinition of metal features, including an electrically continuousground plane across an area of a few wavelengths or more on a side atthe top end of the frequency of operation may be required.

Copper is an excellent electrical conductor at the frequencies ofinterest for wafer-scale phased array antennas, such as in themillimeter-wave frequency range, but copper has a significantlydifferent CTE compared to that of a semiconductor wafer or reticle towhich the copper is connected. Because of the size of the interconnectedmetal and semiconductor materials, the size of the ground plane requiredmakes it difficult to have a metal with a thickness greater than 25microns bonded to the semiconductor wafer or reticle for structures morethan a few millimeters. As such, a method to decouple the mechanicalinterface between the two materials will reduce the CTE mismatch stressinduced as the assembly is subjected to a variety of temperatures.

Because of electrical skin depth limiting the penetration of electricfields into the conductors at higher frequencies, copper thicker than 25microns may not be required to pass RF signals, but other factors (suchas required height above a ground plane of the radiating structure of anantenna for radiation efficiency or bandwidth considerations, orprotection of circuits from damage caused by ionizing radiation in spacebased applications) may mean that thicker metal may be more interestingthan common thin-film or printed circuit board metal thickness values.In such cases, there is a desire to make an antenna that providesradiation shielding to an integrated circuit, while also limiting thefront-end loss of the system. This is used to limit single-eventupset-type failures from occurring in a space-based electronic system.

The PolyStrata® process may be a good way of creating such an antennabecause copper is a high-density material; however, copper may not bethe best way of doing this because it has a coefficient of thermalexpansion (CTE) that is different than the bulk CTE of most integratedcircuits. The idea of using tungsten, molybdenum or other metals thathave a low coefficient of thermal expansion to create these antennas maysolve the thermal expansion problem, but these metals may not be aseasily formed as copper by a process such as the PolyStrata® process dueto, for example, limitations of electroplating such metals. Oneadvantage of including tungsten is that it has a density twice that ofcopper, which means that it can roughly provide the same shieldingproperties in half the thickness. This can decrease the overall heightof an antenna assembly on an integrated circuit. Three-dimensionalcopper spring structures made using PolyStrata® fabrication technologycan address the CTE problems present in applications ranging from waferlevel packaging to wafer level phased array constructions.

If the passive PolyStrata® ground plane circuitry of the antenna arraybehaves mechanically as a continuous copper slab, the thermal stressinduced by different rates of expansion between the semiconductor chipor wafer and PolyStrata® circuitry may cause the terminal connections toeither fail or cause the semiconductor wafer to crack due to thermalexpansion mismatch between the metal and semiconductor. The proposeddisclosure attempts to solve this problem by mechanically isolating eachelements of the array with membranes (or springs) 1112, FIGS. 15-17,while keeping the electrical and high frequency performance intact. Atypical two dimensional spring will result in RF scattering and unwantedantenna behavior. Other fields of use for this technique and suchstructures may include any focal plane array where a two-dimensionalpattern of pixels with a transducer and processing electronics at everypixel is required (at microwave or millimeter-wave frequencies thesetransducers are antennas, but these could be ultrasound transducers orinfrared detectors, among other things). Although not a phased array,passive millimeter-wave imaging arrays also have repeating unit cellswith electronics for each pixel and an antenna as a transducer.Alternatively, the CTE-compensating features in accordance with thepresent invention may be used to conform the array across a surface thathas some amount of non planarity where electrical connections must bemaintained across a wide area. Hence the spring-like features joiningunit cells or die can operate not only in one plane, but compensate fornon planarity or curvature in the axis orthogonal to the plane in whichthey are formed.

FIG. 18 shows a completed antenna array with antenna radiators 1110connected to the signal conductors 1104 of the ground plane array 1100of FIG. 15. Although the signal conductors 1104 are shown to connect tothe center of the antenna radiators 1110, the signal conductors 1104could be located in different positions or multiple signal conductorscould be attached to the antenna radiators 1110. The antenna unit cellscan extend in X and Y beyond what is shown, even if they are connectedto something with a dissimilar CTE because of the CTE decouplingprovided by the membranes or springs 1112.

An exemplary process flow for fabricating the ground plane array 1100shown in FIGS. 15-17 is provided in a step-by-step fashion in FIGS.18A-18L, and an exemplary process flow for fabricating an antenna array1800 is shown in FIGS. 18M-18O. The build steps are illustrated in anX-Z plane cross section. FIGS. 18A-18B show a photoimageable photoresist2002 either laminated or spin coated over a temporary carrier substrate2001. The photoresist 2002 is exposed to UV light, and a pattern isdeveloped/formed by removing regions of photoresist using aphoto-developer liquid. Electrode terminals 2003 are plated in locationswhere the photoresist 2002 has been removed. FIGS. 18C and 18D depictsimilar process steps to deposit or plate more metal and routingcircuits. In FIG. 18C, photoresist is deposited in a relatively thickerlayer, patterned, and non-desired portions removed to provide cavitiesdefined by the remaining photoresist 2004. Metal 2005 is then depositedin the regions between the remaining photoresist 2004 to provide aground plane structure, FIG. 18D. Dielectric supports 2006 are depositedto support the signal conductor on the ground plane metal 2004 inanticipation of future removal of the remaining photoresist 2005, FIG.18E. In the Poly Strata® process, the supports 2006 arephotopatternable.

FIGS. 18F-18G depict similar process steps of photoresist application,UV exposure, photo imaging, removal of non-desired portions of thephotoresist to provide the remaining photoresist 2007, FIG. 18F, withthe spaces in between the remaining photoresist 2004, 2007 plated with ametal 2008, FIG. 18G. Using similar techniques of photoresistapplication, UV exposure, photo imaging, and selective removal ofphotoresist, a ridge of photo resist 2009 is formed over remainingphotoresist 2004, FIG. 18H. A conformal conductive seed layer 2010 isapplied over the upper surface as shown in FIG. 18I in preparation forthe deposition of additional metal. Additional photoresist 2011 may beprovided in areas where metal plating is not desired by selectivelydepositing photoresist application, UV exposure, photo imaging, andselective removal, FIG. 18J. A conformal, thin membrane 2012 of coppermay be applied in the areas where the seed layer 2010 is exposed and notcovered by masking photoresist 2011, FIG. 18K. The thin copper membrane2012 can provide a flexible three-dimensional membrane spring once theunderlying photoresist 2009, 2004 is removed. Were the remainingphotoresist 2004, 2007, 2009 and carrier substrate 2001 removed from thestructure shown in FIG. 18K, the resulting structure would resembleground plane array 1100 of FIGS. 15-17. However, the exemplary processof FIGS. 18A-18O continues in FIGS. 18L-18O to create the antenna array.

Specifically, FIGS. 18L-18N show a further set of photoresist coating,UV exposure, resist removal to provide photoresist 2013, 2014, afterwhich a metal 2015 is provided in the gaps therebetween, where the shapeof the metal 2015 is provided in the shape of antenna radiators 1110,FIG. 18O. All of the remaining photoresist 2004, 2007, 2009, 2013, 2014and carrier substrate 2001 may be removed to provide the antenna arraystructure with ground plane array 2100 as shown in FIG. 18O. Instancesof membranes or springs 2012 are shown as being flush with the topsurface of the ground plane tiles 1102, but this is not necessary forall embodiments of the invention.

The antenna array 1800 may also be attached to a semiconductor chip orwafer 1900 using epoxy, solder or other suitable means, FIG. 19. Thesemiconductor chip or wafer 1900 could also be a ceramic or glasssubstrate, printed circuit board or other medium with an effectivecoefficient of thermal expansion that may be different from that of theantenna array 1800. In addition, although the steps shown in FIGS.18A-18O indicate that the temporary carrier substrate 2001 may beremoved to produce the antenna array 1800, by making the carriersubstrate 2001 permanent, the full device shown in FIG. 19 may becreated monolithically. In this case, semiconductor chip or wafer 1900may be an active wafer, reticle or chip with integrated circuits or itmay be a handle that provides rigidity and a known coefficient ofthermal expansion that is set by the semiconductor chip or wafer 1900.If electrical through vias are put into the semiconductor chip or wafer1900, the device of FIG. 19 could then be assembled into a larger systemwith antenna-element-level electrical connections to amplifiers or otherelectronics in an antenna system, whether an electronically-scannedphased array or otherwise. In addition, the semiconductor chip or wafer1900 could serve as a barrier to prevent underfill material frompenetrating the rest of the device or to provide a solder wick stop ifthe apparatus of FIG. 19 is bonded into a higher level assembly, todeter the flow of solder or other materials that may flow due to wickingback toward the antenna leads or connection points. An underfillmaterial may be used to improve the reliability of the connections fromthe device of FIG. 19 to another package, but such materials may flowinto regions they are not intended to penetrate.

Additionally, using multiple layers for the springs 2012 may suppressunwanted electromagnetic modes that may be supported in regions of airor vacuum between the membranes springs 2012 and semiconductor chip orwafer 1900. These modes may come from energy that leaks through themembranes or springs 2012, as it may not be physically continuous,although it is designed to be electrically continuous. The effect ofthese undesirable modes may appear or disappear depending on theelectronic scanning conditions of the antenna array. This caneffectively increase the frequency at which these electromagnetic modesare supported beyond the frequency band of interest for a givenapplication.

In addition, the three-dimensional membrane 2012 formation, comprisingthe steps of FIGS. 18H-18L for example, two-dimensional springs 1112-2may be provided between ground plane tiles 1102-2 with center conductors1104-2, which springs 1112-2 may not be as efficient either mechanicallyor electrically, but nevertheless represents another embodiment of thepresent invention for providing mechanical decoupling while maintainingelectrical connections, FIG. 20. The 2-dimensional springs 1112-2 havinga serpentine shape and can provide similar methods of CTE decoupling canbe provided as has been described in FIGS. 15-19; however, the aspectratio of the metal and gap definition attainable using a particularfabrication process may constrain the ability of the designer to createsprings 1112-2 with minimal impact on the overall performance of theantenna array or circuit. This is due to the additional inductanceinherent in the springs 1112-2 compared to the springs 1112.

In addition, the ground plane tiles 1102-2 and springs 1112-2 can servea dual purpose. First, the ground plane tiles 1102-2 and springs 1112-2may provide an essentially electrically continuous ground plane over thefrequencies of interest. The features of the springs 1112-2 and the gapsmay be sized to be electrically small compared to the operatingwavelength, so the ground plane of tiles 1102-2 appears continuous tothe antenna elements. An electrically continuous ground plane can beimportant to the antenna's electrical performance. Second, the springfeatures allow for thermal expansion mismatch between a mainly-copperpart (e.g., PolyStrata® part) and a substrate with significantlydifferent thermal expansion, e.g., silicon, SiC, alumina, LowTemperature Cofired Ceramic (LTCC), etc. The springs 1112-2 may allow apart and/or a substrate adjoined thereto to thermally expand in-planewith different rates. The springs 1112-2 can flex to allow theindividual ground plane tiles 1102-2 to move relative to one anotherwithout putting undue stress either within the ground plane itself.Additionally, the springs 1112-2 can flex to deter stress between theground plane and attached structures, including, for example: a metalpart (e.g., Poly Strata® part); the bonded electrical junction betweenthe part and a substrate below, e.g., a wafer; and/or, an antennaradiator structure. The effect of the springs 1112-2 on a bondedelectrical joint, such as that to a semiconductor wafer, can have anegligible effect on the joint's fatigue life, and can survive therequired number of thermal cycles that would be expected duringqualification testing and on-orbit lifetime for a typical spacecraftmission.

FIG. 21 schematically illustrates a modification to the apparatus shownin FIG. 18 to improve radiation shielding across the entire devicesurface. By making a jog 1120 along the path of the center conductor1104, the regions of lowest line-of-sight radiation shielding havehigher shielding levels. Item 1122 is a shield staggering feature in theCTE decoupling structure region. This lowers the effective shielding inthose areas where the staggering occurs, but if the gaps betweenmaterial of adjacent unit cells can be minimized, the reduction ofshielding is minimized. With reference to FIG. 19, if the radiationshielding capability of the antenna array for the circuits on 1900 isimportant, it is possible to ensure those circuits most sensitive toionizing radiation damage are not placed directly under the U-shapedspring regions 1112 or other areas with less shielding.

In yet a further aspect of the present invention, an array of antennaradiators may be provided using a singulation technique as illustratedin FIGS. 22A, 22B. A continuous array 2200 of antenna radiators may beprovided that may include a bottom-side metal pattern 2220, a top-sidemetal pattern 2230, and circuit board 2240, FIG. 22A. The bottom-sideand top-side metal patterns 2220, 2230 may be generally periodic andrepeat on the antenna unit cell pitch. It is possible to not have apattern on one or both sides of the board 2240, and there could bemultiple pads on one side of the board (for instance in a case where twopads from the bottom-side metal pattern are capacitively couplingthrough the board 2240 to the topside metal pattern 2230). Thecontinuous radiator array 2200 may be bonded to the ground plane array1100 shown in FIG. 15 or the ground plane 1810 of FIG. 18, FIG. 22B. Theindividual unit cells may be separated from each other by laser ablationor using a dicing saw to decrease the amount of continuous circuit boardmaterial to reduce stress induced by CTE differences over the entirelength of the continuation array 2200, as the antenna circuit boardmaterial is broken into unit-cell-sized pieces, FIG. 22B. By bonding asingle continuous radiator array 2200 to the rest of the structurebefore singulation of the unit-cell-size pieces, there are fewerassembly steps than if each unit-cell-sized piece were assembledindividually. As the size of the gap between adjacent unit cells can besmall (on the order of 25 microns), the overall electrical effect ofmaking the circuit board material discontinuous can be minimal.

These and other advantages of the present invention will be apparent tothose skilled in the art from the foregoing specification. Accordingly,it will be recognized by those skilled in the art that changes ormodifications may be made to the above-described embodiments withoutdeparting from the broad inventive concepts of the invention. Forexample, while fabrication via PolyStrata® technology has beenmentioned, other methods of photolithography-based fabrication, 3 dprinting or other fabrication techniques could be employed in accordancewith the present invention. Alternatively, the previous discussion hasfocused on the spring-like features being included in the material thathas the higher CTE; however, through bulk micromachining (or othermethods), the spring features could be integrated into the lower-CTEdevice bonded (such as silicon). It should therefore be understood thatthis invention is not limited to the particular embodiments describedherein, but is intended to include all changes and modifications thatare within the scope and spirit of the invention as set forth in theclaims.

What is claimed is:
 1. An microelectronic structure having CTEcompensation for use in wafer-level and chip-scale packages, comprisinga plurality of substrate tiles each having a generally planar uppersurface, the upper surfaces of the tiles disposed within a common planeto provide a generally planar grid of the tiles, each respective pair ofadjacent tiles having a gap disposed therebetween and a spring structurespanning the gap and connecting the adjacent tiles, the spring structureconfigured to permit movement of the adjacent tiles relative to oneanother to provide compensation for thermal expansion or contraction ofthe tiles.
 2. The microelectronic structure of claim 1, wherein thesubstrate tiles comprise a semiconductor material.
 3. Themicroelectronic structure of claim 1, wherein the substrate tilescomprise metal.
 4. The microelectronic structure of any one of thepreceding claims, wherein the spring structure comprises a membrane. 5.The microelectronic structure of claim 1, wherein the spring structurecomprises a 2-dimensional serpentine structure.
 6. The microelectronicstructure of claim 1, wherein the spring structure comprises a metal. 7.The microelectronic structure of claim 1, wherein the spring structurecomprises a U-shaped membrane having a longitudinal axis that isdisposed parallel to an edge of the upper surface of the selected tileto which the u-shaped membrane is attached.
 8. The microelectronicstructure of claim 1, wherein the spring structure comprises anon-planar structure having a central region that extends downward intothe gap.
 9. The microelectronic structure of claim 1, wherein the springstructure comprises a non-planar structure having a central region thatextends upward above the common plane.
 10. The microelectronic structureof claim 1, wherein the spring structure is attached to the uppersurfaces of the adjacent tiles.
 11. The microelectronic structure ofclaim 1, wherein surfaces of the gap comprise crystallographic planes ofa semiconductor material.
 12. The microelectronic structure of claim 1,comprising a dielectric material disposed on the common plane anddisposed within the gap.
 13. The microelectronic structure of claim 1,comprising a device layer attached to the common plane.
 14. Themicroelectronic structure of claim 13, wherein the device layercomprises one or more of resistors, capacitors, inductors, andthree-dimensional metal/dielectric structures.
 15. The microelectronicstructure of claim 14, wherein the three-dimensional metal/dielectricstructures include one or more of coaxial waveguides, antennas,Wilkinson combiner/dividers, Gysel combiner/dividers, and filters. 16.The microelectronic structure of claim 13, wherein the device layer isattached to the common plane with the dielectric material disposedtherebetween, and wherein the device layer is electrically connected toa selected one of the tiles by one or more vias extending through thedielectric material.
 17. The microelectronic structure of claim 1,wherein the tiles each comprise a lower surface opposing the uppersurface and comprising a stretcher material disposed on the lowersurfaces of the tiles.
 18. The microelectronic structure of claim 1,wherein the plurality of tiles each comprise multiple layers of metaldisposed parallel to the upper surface.
 19. The microelectronicstructure of claim 1, comprising a plurality of antenna radiatorstructures disposed above the upper surfaces of the tiles.
 20. Themicroelectronic structure of claim 1, wherein the plurality of tiles iselectrically continuous.
 21. The microelectronic structure of claim 1,wherein the tiles each comprise a lower surface opposing the uppersurface and comprising a semiconductor chip or wafer electricallyconnected to the lower surface.
 22. The microelectronic structure ofclaim 21, wherein the wafer comprises one or more of ceramic substrate,a glass substrate, and a printed circuit board.
 23. A method of forminga three-dimensional microstructure by a sequential build process,comprising: disposing a plurality of layers over a substrate, whereinthe layers comprise one or more layers of a conductive material and oneor more layers of a sacrificial material, thereby forming a structureabove the substrate, comprising: a plurality of conductive tiles formedof the conductive material, each tile having a generally planar uppersurface, the upper surfaces of the tiles disposed within a common planeto provide a generally planar grid of the tiles, each respective pair ofadjacent tiles having a gap disposed therebetween and a spring structurespanning the gap and connecting the adjacent tiles, the spring structureconfigured to permit movement of the adjacent tiles relative to oneanother to provide compensation for thermal expansion or contraction ofthe tiles.
 24. The method of claim 23, wherein the spring structure isformed of the conductive material.
 25. The method of claim 23,comprising removing the sacrificial material.
 26. The method of claim23, comprising removing the substrate.
 27. The method of claim 23,wherein the spring structure comprises a membrane.
 28. The method ofclaim 23, wherein the spring structure comprises a 2-dimensionalserpentine structure.
 29. The method of claim 23, wherein the springstructure comprises a U-shaped membrane having a longitudinal axis thatis disposed parallel to an edge of the upper surface of the selectedtile to which the u-shaped membrane is attached.
 30. The method of claim23, wherein the spring structure comprises a non-planar structure havinga central region that extends downward into the gap.
 31. The method ofclaim 23, wherein the spring structure comprises a non-planar structurehaving a central region that extends upward above the common plane. 32.The method of claim 23, wherein the spring structure is attached to theupper surfaces of the adjacent tiles.
 33. The method of claim 23,wherein the step of disposing a plurality of layers over a substratecomprising disposing one or more layers of a dielectric material. 34.The method of claim 23, wherein the structure formed above the substratecomprises a plurality of antenna radiator structures disposed above theupper surfaces of the tiles.
 35. The method of claim 23, wherein thesubstrate comprises one or more of ceramic substrate, a glass substrate,and a printed circuit board.
 36. The method of claim 23, comprisingelectrically connecting a device layer to the common plane.
 37. Themethod of claim 36, wherein the device layer comprises one or more ofresistors, capacitors, inductors, and the three-dimensionalmetal/dielectric structures.
 38. The microelectronic structure of claim37, wherein the three-dimensional metal/dielectric structures includeone or more of coaxial waveguides, antennas, Wilkinsoncombiner/dividers, Gysel combiner/dividers, and filters.
 39. The methodof claim 23, wherein the tiles each comprise a lower surface opposingthe upper surface and comprising electrically connecting a semiconductorchip or wafer to the lower surface.
 40. A method of forming athree-dimensional microstructure by a sequential build process,comprising: providing a substrate having opposing upper and lowersurfaces, with a trench extending from the lower surface to a regionproximate the upper surface; providing a stretcher layer on the trenchand lower surface of the substrate; expanding the stretcher layerlinearly along a direction parallel to the lower surface of thesubstrate to separate the substrate into first and second substrateportions divided at the location of the trench providing an expandedtrench region; and providing a dielectric material in the expandedtrench region.
 41. The method according to claim 40, wherein the step ofproviding a dielectric material includes providing the dielectricmaterial on the upper surface of the first and second substrateportions.
 42. The method according to claim 41, comprising providing aplurality of conductive vias through the dielectric material, the viasin electrical communication with the upper surface of at least one ofthe first and second substrate portions.
 43. The method according toclaim 42, comprising providing a device layer over the dielectricmaterial, the device layer including at least one electronic componentin electrical communication with a selected one of the vias.
 44. Themethod according to claim 43, wherein the electronic component comprisesone or more of resistors, capacitors, inductors, and three-dimensionalmetal/dielectric structures.
 45. The method according to claim 44,wherein the three-dimensional metal/dielectric structures include one ormore of coaxial waveguides, antennas, Wilkinson combiner/dividers, Gyselcombiner/dividers, and filters.